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Materials and processes for innovative next-generation devices
Researchers & Research Theme
Phase I Phase II Phase III

2009 Researchers

Hideo KAIJU Hiroshi KUMIGASHIRA Yasushi TAKAHASHI
Katsuhiro TOMIOKA Koji NAKANO Hiroyuki NAKAMURA
Jiro NISHINAGA Yutaka NOGUCHI Suguru NODA
Masataka HIGASHIWAKI Tomoki MACHIDA Hiroshi YAMAMOTO

Control of Si/III-V super-heterointerface and development of nanowire-based tunneling FETs

photo Katsuhiro TOMIOKA
Research Site
JST PRESTO Research Fellow , Graduate School of Information Science and Technology, Hokkaido University
Research Results
Conventional MOSFETs have theoritical limit in subthreshold characteristic (SS) resulting from carrier diffusion (SS > 60 mV/dec). The goal of this project to fabricate steep-slope nanowire-based FET by controlling Si/III-V heterojunctions without misfit dislocations, which can be achieved with nano-heteroepitaxial methods.



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