Ultra Depedable VLSI by collaboration of formal verifications and architectural technologies
Shuichi Sakai (The University of Tokyo / Professor)
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For precise and errorless design of VLSI which is one of the most primary elements in today's information-centric soceity, this project will comprehensively develope dependability technologies from circuit design to system architectures.
It includes new formal verification techniques, introductions of field programmable circuts for the test-phase corrections, the circuit which prevents timing errors and architectural technologies to prevent parmanent failures.
These tehniques will be tightly integrated and will substantially increase VLSI dependability.
The research results will include the new design tools, new digital circuits and architectures which will be fed back to industry and will construct the basis to reinforce the industrial competitiveness in the area of semiconductors, home electronics, automobiles and aerospace technologies.
Kick-off Meeting (October 2007) (PDF 516kB)
2008 Program Review (October 2008) (PDF 1,031kB)
DVLSI Workshop 2008 (December 2008) (PDF 1,092kB)
2009 Program Review (April 2009) (PDF 1,048kB)
DVLSI Workshop 2009 (December 2009) (PDF 875kB)
2010 Program Review1 (June 2010) (PDF 1,219kB)
2010 Program Review2 (October 2010) Prof. Fujita The University of Tokyo (PDF 693kB)
2010 Program Review2 (October 2010) Associate Prof. Goshima The University of Tokyo (PDF 183kB)
DVLSI Workshop 2011/3 (March 2011) (PDF 899kB)
DVLSI Workshop 2011/12 (December 2011) (PDF 1,1633kB)
DVLSI Workshop 2012/6 (June 2012) (PDF 577kB) (English document)
DVLSI International Symposium 2012/12 (December 2012) (PDF 2,175kB) (English document)
2007 Annual Report (PDF 2,177kB)
2008 Annual Report (PDF 1,810kB)
2009 Annual Report (PDF 1,997kB)
2010 Annual Report (PDF 3,140kB)
2011 Annual Report (PDF 872kB)