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Dipendable SRAM Techniques for Highly Reliable VLSI System

Principal Investigator
Masahiko Yoshimoto (Kobe University / Professor)

Research Theme:
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} The goal of the project is to develop design techniques for scaled SRAM to enhance a dipendability of VLSI system in deep sub-deci micron era and beyond. To overcome several error factors including process variation, operating condition fluctuation, performance degradation by aging and soft error phenomena, we will develop fundamental techniques to predict failure situations, to sustain normal state of operation and to avoid fatal errors. Then by unifying the above techniques, an autonomous dipendable memory platform will be established. Finally effectiveness of proposed methods will be verified for car-electronics application using virtualization techniques.

Open Documents

2008 Program Review (October 2008) (PDF 89kB)
DVLSI Workshop 2008 (December 2008) (PDF 180kB)
2009 Program Review (April 2009) (PDF 829kB)
DVLSI Workshop 2009 (December 2009) (PDF 75kB)
2010 Program Review1 (June 2010) (PDF 809kB)
2010 Program Review2 (October 2010) Senior Researcher Oho Hitachi Central Research Lab. (PDF 472kB)
DVLSI Workshop 2011/3 (March 2011) (PDF 74.9kB)
DVLSI Workshop 2011/12 (December 2011) (PDF 419kB)
DVLSI Workshop 2012/6 (June 2012) (PDF 857kB) (English document)
DVLSI International Symposium 2012/12 (December 2012) (PDF 226kB) (English document)

Annual Reports

2008 Annual Report (PDF 1,012kB)
2009 Annual Report (PDF 1,107kB)
2010 Annual Report (PDF 861kB)
2011 Annual Report (PDF 4,897kB)

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