Modeling, Detection, Correction and Recovery Techniques for Unified Dependable Design
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Principal Investigator Hiroto Yasuura (Kyushu University / Professor) Research Theme:
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The goal of the project is to establish a design flow in system and RT levels for dependable digital VLSI. We will define models errors and indexes of dependability,
and develop techniques to evaluate the indexes and to improve them. We will implement the techniques as design and analysis tools, and combine the tools into an existing design flow to make
a prototype of design flow in which designers can consider tradeoffs among cost, performance, power consumption and dependability.Subjects: Closeup by click
We establish an efficient design flow to analyze tolerance of soft error which become high risk due to neutron or alpha particles in very deep submicron.Products: A tool chain to analyze stochastically soft error rate and to estimate soft error tolerance of circuits in system level to circuit level based on device characteristics of cells obtained by device level analysis. Tool Chain Charactaristics: Analysis of soft error tolerance for huge system with some hundred million transistors based on device characteristics obtained by conventional device simulator in efficient time. Contributions: 1. Designers can estimate soft error tolerance in system and RT level for digital VLSI and consider tradeoffs among cost, performance, power consumption and dependability. 2. Quantitative estimation of soft error tolerance for applications which require high dependability such as airplane and automotive. (Stress test for digital VLSIs) 3. It is an important issue that we build consensus on use of proposed techniques among VLSI users in industry segment. Principal joint researcher
Yusuke Matsunaga (Kyushu University / Associate Professor)Toshinori Sato (Fukuoka University / Professor) |
Open Documents
Kick-off Meeting (October 2007) (PDF 346kB)
2008 Program Review (October 2008) (PDF 103kB)
DVLSI Workshop 2008 (December 2008) (PDF 173kB)
2009 Program Review (April 2009) (PDF 593kB)
DVLSI Workshop 2009 (December 2009) (PDF 142kB)
2010 Program Review1 (June 2010) (PDF 822kB)
2010 Program Review2 (October 2010) Associate Prof. Matsunaga Kyusyu Univ. (PDF 111kB)
2010 Program Review2 (October 2010) Associate Prof. Sugihara Toyohashi Univ. Technology (PDF 93kB)
DVLSI Workshop 2011/3 (March 2011) (PDF 141kB)
DVLSI Workshop 2011/12 (December 2011) (PDF 393kB)
DVLSI Workshop 2012/6 (June 2012) (PDF 173kB) (English document)
DVLSI International Symposium 2012/12 (December 2012) (PDF 2,053kB) (English document)
Annual Reports
2007 Annual Report (PDF 694kB)
2008 Annual Report (PDF 351kB)
2009 Annual Report (PDF 316kB)
2010 Annual Report (PDF 269kB)
2011 Annual Report (PDF 484kB)
