Currently, in a qubit controller operating at room temperature, a front-end analog RF part (Fig. 1) for transmitting and receiving microwave control signals consists of compound semiconductor devices, bipolar devices, and numerous discrete components with excellent high-frequency and low-noise characteristics, resulting in large mounting size and high-power consumption. To increase the number of qubits in the future, it is necessary to drastically reduce the mounting size and power consumption of the front-end analog RF part. In this project, PLL (Phase Locked Loop), transmitter (TX), and receiver (RX), which are essential functional blocks in the front-end analog RF part, have been developed utilizing advanced CMOS process technologies to ensure proper operation at room temperature, with the goal of miniaturization and low power consumption. In addition, the improvement of isolation between transmitter and receiver, which is a challenge in integration, was examined.

Based on the evaluation results of the PLL and transceiver (TX/RX) test chips (22 nm FDSOI CMOS) developed by fiscal year 2024, design guidelines for the integration of the front-end analog RF section were established.
To address long-term phase fluctuations, a rubidium oscillator with extremely high frequency stability was employed as the reference signal source, and the PLL comparison frequency was set relatively high, in the range of 500 MHz to 1 GHz. An all-digital PLL (ADPLL) architecture using a bang-bang phase detector (BB-PD) was adopted. The BB-PD has a simple circuit structure and can operate at high frequencies such as 1 GHz using advanced CMOS process technologies, while eliminating the need for analog circuits and reducing temperature-dependent steady-state phase error. For long-term phase fluctuation evaluation, 0.12° rms was confirmed for the 10 GHz ADPLL alone in a measurement system using a rubidium oscillator as the reference signal source, with a measurement time of 1,000 seconds and a measurement time resolution of 40 milliseconds (Fig. 2).　

For the 10 GHz LNA (Low Noise Amplifier), which is a key building block of the receiver, a noise suppression circuit topology was introduced, and a high‑Q transistor structure that significantly reduces parasitic capacitances (Rg and Cds) was proposed. Furthermore, miniaturization of the LNA was achieved by magnetically coupling the ESD protection shunt inductor with the matching inductor.
For the 10 GHz PA (Power Amplifier), which is a key building block of the transmitter, a high‑Q transistor structure with reduced parasitic capacitances (Cgs, Cds, and Cgd) was proposed to minimize output signal loss. Furthermore, to suppress unstable behavior caused by parasitic elements under high output power conditions, a differential cross-coupled circuit employing neutralization capacitors was adopted as the PA topology.
To achieve high TX-RX isolation, a clover‑shaped inductor that suppresses magnetic flux leakage in all directions was employed in the PA. Similarly, an inductor structure that suppresses magnetic flux leakage from the transmitter was adopted in the LNA. Furthermore, in both the transmitter and receiver circuits fully differential architectures were employed.
Measurement results of the transceiver evaluation test chip confirmed an LNA with a noise figure of approximately 2.5 dB (Fig. 3) and a PA delivering output power 10 dBm at 10 GHz, while operating with approximately one tenth the power consumption of a conventional transceiver implemented using discrete components. Furthermore, TX-RX isolation greater than 70 dB was achieved (Fig. 4).
From these results, the effectiveness of the proposed design guidelines was confirmed.