We aim to develop devices for building scalable systems using ASICs (application-specific integrated circuits) and SoCs (systems-on-chip) capable of stable operation at cryogenic temperatures (4K). We conducted fundamental research on cryogenic-capable DRAM (dynamic random-access memory) and wiring models for cryogenic environment. Furthermore, we integrated four circuit blocks—a digital circuit (sine wave generator), a PLL (phase-locked loop), a DAC, and an ADC—onto a cryogenic-capable SoC (system-on-a-chip) and confirmed their normal operation at cryogenic temperatures (Fig.1).

In items 1, 4, and 5, the Register Transfer Level (RTL) of the digital signal processing processor (DSP) already implemented on the FPGA was modified for use with an ASIC, and some calculations were converted to floating-point arithmetic with smaller bit widths. Using SRAM designed for 4K, this RTL was converted into an ASIC using a 22nm bulk process, and the normal operation of some circuits at room temperature was confirmed. A GCDRAM(Grain Cell DRAM), usable as pseudo-SRAM at cryogenic temperatures, was prototyped, and its retention time in a cryogenic environment was confirmed via measurement to be in the order of milliseconds.
In item 2, device modeling and design evaluation of elemental circuits were continued toward the realization of RF (radio frequency) front-end circuits for cryogenic applications. Regarding device modeling, the wiring resistance model proposed in 2023 was verified and improved by measurement, and a highly practical model was proposed. While the proposed model achieved higher accuracy than the previous model, it was found that errors still occurred around 4K (Fig.2). For the RF elemental circuits, a clock generation PLL was designed, and its operation at 4K was confirmed by measurement. Furthermore, the RF signal source, local oscillator (LO), mixer, and passive balun (balanced-unbalanced conversion circuit) were designed using a 22nm CMOS process.

In item 3, the DAC designed using the 22nm CMOS process was measured at room temperature and 4K. Additionally, the automated design of an 8-bit DAC was achieved using Bayesian optimization. Since the execution time for the 8-bit DAC circuit was less than 6 hours, the issue of execution time when expanding to a 12-bit DAC became a future challenge.
In item 4, to realize a performance-scalable, high-speed ADC operating on cryogenic temperatures, an 8-channel time-interleaved ADC was designed using a 22nm bulk CMOS process (Fig.3a). Additionally, a channel mismatch correction circuit, which is a challenge during time-interleaved operation, was designed, and test chips were created (Fig.3b). The created ADC was confirmed to operate normally at room temperature and in a liquid helium (4.2K) environment, successfully developing an ADC with 10-bit resolution and a sampling rate of 2GS/s.
We also conducted actual measurements of the SoC, which integrates the elemental circuits from items 1 to 4, at extremely low temperatures. Although the DAC exhibited some performance limitations, we confirmed that it was functioning normally.