Progress Report

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Development of a Scalable, Highly Integrated Quantum Error Correction System[3] Scalable Classical-Quantum Interface with Optical/Cryo CMOS Integrated Circuits

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Progress until FY2025

1. Outline of the project

To realize a scalable quantum computer, it is essential to efficiently transmit large volumes of data between classical and quantum circuits.  This requires reducing the amount of wiring between the room-temperature and cryogenic environments. In Item 3, as shown in Figure 1, we will develop an optical/Cryo CMOS integrated circuit that operates at the classical-quantum boundary to realize highly efficient information transmission. As key technologies, we are developing items (a) through (d) shown in Figure 1. This year, we (a) proposed a low-cost qubit control architecture, (b) measured low-temperature characteristics for optical integrated circuits, (c) developed PDKs for Cryo CMOS circuits, and (d) developed design techniques for Cryo CMOS circuits.

Fig.1
Figure 1: Overview of Item 3

2. Outcome so far

(a)Quantum control architecture for Cryo environment

We proposed a low-cost qubit controller architecture (Figure 2) and further extended it to an optoelectronic circuit architecture. Numerical evaluations demonstrated that the proposed architecture can significantly reduce power consumption compared with conventional CMOS-based qubit controllers.

Fig.2
Figure 2: Low-cost architecture
(b) Low-temperature measurements of optical integrated circuits for the classical-quantum interface

Optical integrated circuits showed room-temperature-like switching in liquid nitrogen (Figure 3) and liquid helium.

Fig.3
Figure 3: Optical switch characteristics
(c) Development of PDK for Cryo CMOS

Based on experimental measurements at 7 K, we modeled the body-bias dependence of the current characteristics in 180-nm transistors using BSIM4 and constructed an FBB-aware standard-cell library across 100 supply and body-bias conditions. Using this library, we demonstrated with a RISC processor that voltage scaling combined with FBB improves the power-delay product by approximately 70% compared to room-temperature operation. We also confirmed normal AES operation at 4.2 K, demonstrating the practicality of the PDK (Figure 4).

Fig.4
Figure 4: Setup and observed waveforms
(d) Cryo-Integrated Circuit Design Technology

Using an exhaustive-search-based surface code decoder as an example, the suitability of different circuit architectures for cryogenic operation was investigated. First, the impact of edge-weight quantization on the logical error rate was evaluated, showing that reducing edge weights to a fixed 6-bit representation maintained correction accuracy equivalent to the optimal solution within the assumed physical error-rate range.

Regarding the architectures, SRAM-based decoder designs increase memory accesses as error patterns become more complex, resulting in longer delays. In contrast, a hard-wired logic design, where edge weights are embedded as wiring connections, eliminates memory-access bottlenecks and enables constant-latency operation at low temperatures.

Fig.5
Figure 5: Logical error rate vs. quantization bit width (Nb)

3. Future plans

We will integrate the acquired findings to develop a prototype of a scalable classical-quantum interface using optical/cryo-CMOS integrated circuits.

Cryo:
Cryogenic,
PDK:
Process Design Kit,
RISC:
Reduced Instruction Set Computer,
AES:
Advanced Encryption Standard,
BSIM4:
Berkeley Short-channel IGFET Model 4
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