Progress Report
Last updated:
Development of a Scalable, Highly Integrated Quantum Error Correction System[1] Error Correction Algorithm for Hardware and Backend System with FPGA
Progress until FY2025
1. Outline of the project
The aim of this R&D Item is to develop an error correction backend system that can perform error syndrome analysis required for error correction at high speed and low latency. To this end, the following three tasks are being implemented. Task 1 is to develop error correction hardware for fast, low latency, and scalable error syndrome analysis, and an error correction backend (BE) system using an FPGA cluster. In Task 2, to investigate the performance improvement of the BE system by optimizing the hardware implementation method, we study the ASIC implementation of the main part of the quantum error correction (QEC) core circuit and evaluate its performance. In Task 3, we develop a high-performance and reliable interconnection network technology between the quantum front-end (FE) developed in Item 2 and our BE, as well as a reliable FPGA cluster technology to prepare for larger-scale BE.
2. Outcome so far
1. Error Correction Hardware and FPGA Clusters
We developed and optimized the Syndrome Subgraph Algorithm (SSA) for efficient execution on FPGA hardware, further extending it for parallel processing across multiple FPGAs. Evaluations using a custom software simulator confirmed that algorithm optimization and parallelization significantly improved the logical error rate. We implemented this algorithm as a QEC circuit module on an FPGA, verified functionality and assessed resource consumption and operating frequency relative to code distance (Fig.1). For multi-FPGA parallelization, we split the algorithm such that no bidirectional inter-FPGA communication is required in tight loops, minimizing latency while distributing workload. Additionally, we have installed an FPGA cluster with 32 state-of-the-art FPGAs to implement our QEC decoder parallelized with multiple FPGAs.
2. Evaluation of QEC Cores for ASICs
We investigated how the architecture and achievable performance of QEC cores change when implemented as ASICs. We developed the RTL implementation and estimated the power consumption, latency, and area of each component circuit. In addition, for the quantum error-correcting code decoder, which serves as the core of the QEC system, we proposed an optimized microarchitecture and conducted the fabrication and experimental evaluation of a test chip using a 22-nm CMOS process (Fig.2). Furthermore, we also explored ASIC-based QEC cores for quantum computing platforms other than superconducting qubits.
3. Realization of a Dependable Error Correction Backend for the FE-BE demonstration system
We have demonstrated that the packet aggregator reduces the bandwidth requirement between FE and BE in the proof-of-concept system. The aggregator has the same or lower latency as commercial Ethernet switches, so it can help extend the time window available for the QEC process in the BE. We further extended the aggregator to a dedicated, FPGA-based Ethernet switch for BE, for efficient communication among the FPGAs in BE. The picture above is a testbench for our new, many-to-many, ultra-low-latency data transfer system intended to replace Ethernet with a custom protocol to maximize the performance of the QEC system (Fig.3).
3. Future plans
To realize a QEC BE system that can handle scalable processing with multiple FPGAs, we have been developing the basic technical elements of the system, such as QEC, its hardware design, FPGA SoC, and a network between FE and BE. In the future, we plan to adapt our BE to target not only superconducting qubits, but also neutral atom quantum computers. Additionally, we will work on performing logical qubit operations, going beyond quantum memory experiments.