R&D Project
Goal 6 R&D Projects (Selected in 2020)Development of Integration Technologies for Superconducting Quantum Circuits
Project manager (PM)YAMAMOTO TsuyoshiResearch Fellow, Secure System Platform Research Laboratories, NEC Corporation
Summary of the project
To accelerate the research and development of superconducting quantum computers, we will develop elemental hardware technologies required for large-scale and highly integrated superconducting qubits. Thereby, we aim to realize a large-scale superconducting quantum computer by 2050.
To further scale up the ~100-qubit circuits currently developed around the world, the problem of the explosive increase in the number of wiring between the qubit chip and the control electronics must be solved. In this project, we aim to solve this problem by using cryoelectronics technologies such as single-flux quantum circuits and high-density wiring technology using flip-chip mounting.
In addition, to reduce the hardware requirements for realizing a quantum computer, such as the number of physical qubits and the number of wirings, we will develop high-coherence qubits and implement a new quantum error-correcting code called a bosonic code.
Milestone by the year 2030
Realizing quantum error correction using a method that can be applicable to the large-scale integration. The achievement of this milestone demonstrates the feasibility of quantum error correction at low temperatures and establishes a basic road map for the next decade to integrate large-scale qubits based on a basic stacked structure of qubit chips and classical circuit chips for qubit control and readout.
Milestone by the year 2025
We will realize low-temperature operation of the peripheral circuits and show the possibility of large-scale integration of superconducting qubits on a scale required for the error correction. The achievement of this milestone demonstrates that cryoelectronics can be used to control qubits with high precision.
This will lead to the next step of qubit readout using cryoelectronics and the stacking of qubit chips with classical circuit chips including cryoelectronics.
R&D theme progress reports
Performers
| Theme [1] | YAMAMOTO Tsuyoshi | NEC Corporation |
|---|---|---|
| Theme [1] | INOMATA Kunihiro | National Institute of Advanced Industrial Science and Technology |
| Theme [1] | KOSHINO Kazuki | Institute of Science Tokyo |
| Theme [1] | YOSHIHARA Fumiki | National Institute of Information and Communications Technology |
| Theme [1] | YAMASHITA Taro | Tohoku University |
| Theme [1] | KONOTO Makoto | National Institute of Advanced Industrial Science and Technology |
| Theme [1] | SAITO Shiro | Nippon Telegraph and Telephone Corporation |
| Theme [1] | NOGUCHI Atsushi | RIKEN |
| Theme [1] | TSAI Jaw-Shen | Tokyo University of Science |
| Theme [2] | YOROZU Shinichi | RIKEN |
| Theme [2] | SAITOH Masamichi | ULVAC Cryogenics Inc. |
| Theme [2] | FUJIWARA Yuya | ULVAC, Inc. |
| Theme [2] | NAKAGAWA Hisashi | National Institute of Advanced Industrial Science and Technology |
| Theme [2] | UZAWA Yoshinori | National Astronomical Observatory of Japan |
| Theme [2] | KAWAKAMI Akira | National Institute of Information and Communications Technology |
| Theme [3] | TANAKA Masamitsu | Nagoya University |
| Theme [3] | MIYAMURA Makoto | NanoBridge Semiconductor, Inc. |
| Theme [3] | TADA Munehiro | Keio University |
| Theme [3] | UCHIDA Ken | The University of Tokyo |
| Theme [3] | ISHIKURO Hiroki | Keio University |
| Theme [3] | NEGORO Makoto | The University of Osaka |
| Theme [3] | INOUE Koji | Kyushu University |
PDF Download
- Summary of the project (237KB)
- Progress Report (Download all) (574KB)