Progress Report
Last updated:
Development of Integration Technologies for Superconducting Quantum Circuits[3] Research and development of electronics for quantum error correction
Progress until FY2025
1. Overview
In the typical setup of today's superconducting qubit circuits, a qubit chip placed at cryogenic temperatures and microwave electronics operating at room temperature are connected using one or more coaxial cables per qubit. However, due to limitations in space and cooling power of the refrigerator, this method cannot be scaled-up to tens of thousands of qubits. To solve this problem, this R&D theme aims to develop qubit control and readout electronics that operate as close to the qubit as possible and to break through the wiring bottleneck for integration. In this development, the challenge is how to realize a system that efficiently performs quantum error correction within the limited space and cooling capacity of the refrigerator.
This R&D theme focuses on single flux quantum circuits, which can operate at several tens of GHz and have ultra-low power consumption, and NanoBridge FPGAs, which are highly flexible, capable of advanced processing, and have low power consumption, in order to develop low-temperature electronics systems in which they work together.
2. Outcome so far
① Completion of an Ultra-Low-Power Cell Library Using Single-Flux-Quantum Circuits and Demonstration of High-Frequency Operation in Signal Distribution Circuits
In this project, we have been working to achieve ultra-low power consumption in single-flux-quantum (SFQ) circuits, with the goal of operating them in an environment of approximately 10 mK within the same dilution refrigerator as the qubits. Considering temperature-dependent device characteristics at temperatures below 1 K, we have reduced the critical current and drive voltage of the Josephson junctions used in the SFQ circuits, thereby lowering power consumption to 1/50 to 1/250 of the conventional level. This fiscal year, we expanded our library of SFQ circuit elements (such as wiring and logic gates) organized as “cells,” and completed the library by precisely extracting information on delays, timing constraints, and other factors. We performed on-chip test of a signal distribution circuit composed of the developed cells and confirmed its operation at high frequencies, where particularly careful timing design is required.
② Demonstration of 4K NanoBridge FPGA Operation in a Dilution Refrigerator
To support a variety of error correction algorithms, we are developing an FPGA capable of operating at low temperatures. By the end of last fiscal year, we had completed the fabrication of a cryogenic SoC incorporating a NanoBridge FPGA manufactured using a standard CMOS process (65 nm). This fiscal year, we demonstrated the integrated operation of the signal input/output circuits (LVDS circuits), analog-to-digital conversion circuits, and FPGA circuits mounted on the SoC within the 4 K stage of a dilution refrigerator. Furthermore, by mapping the error-correcting decoder algorithm to the FPGA, we confirmed that it operates at 4 K with performance approximately 15% higher than that at room temperature.
3. Future Developments
Regarding SFQ circuits, we will utilize the library we have developed to design and fabricate control circuits for superconducting qubits, with the goal of demonstrating qubit control.
We will also work on a collaborative operation demonstration of cryogenic electronics that uses a NanoBridge FPGA to control these SFQ circuits.