Progress Report
Development of Integration Technologies for Superconducting Quantum Circuits1. Research and development of qubit circuits for error tolerant quantum computers
Progress by FY2022
1. Overview
One of the hardware challenges in realizing an error-tolerant general-purpose quantum computer is that a large number of physical qubits are required to implement error-correcting codes, and in the case of superconducting qubits, the number is said to be enormous (108) at typical error rates (~0.1%).To solve this problem, this R&D theme will contribute to reducing the number of qubits required to realize an error-resistant general-purpose quantum computer by investigating the causes of errors and developing high-quality qubit manufacturing technology based on this research. In addition, since current manufacturing methods (Electron beam exposure and oblique deposition methods) present challenges in terms of productivity and qubit uniformity for future large-scale circuits, we will develop qubit fabrication technology using optical exposure and stacking processes. We will also conduct exploratory research on bosonic codes, which are expected to enable error-resistant quantum computation with fewer physical qubits than the currently mainstream surface codes, to identify the possibilities and promising schemes. We will also conduct exploratory research on bosonic codes, which are expected to enable error-resistant quantum computation with fewer physical qubits than the currently mainstream surface codes, to identify the possibilities and promising schemes.
2. Results by FY2022
① Development of large-area, high-throughput Josephson junction fabrication technology
Current fabrication of superconducting quantum circuits is typically done using electron beam lithography and angle deposition. However, as circuits become larger in scale and wafers become larger in diameter, the current method poses problems in terms of manufacturing throughput and qubit fabrication variability. To solve these problems, we are developing a superconducting qubit circuit fabrication process that is compatible with state-of-the-art semiconductor processes using 300 mm wafers. This time, qubits were fabricated using optical exposure (ArF immersion) for patterning. The 2% resistance variation at room temperature was achieved for a Josephson junction of the same size as the qubit. The fabricated qubits were evaluated using a 3D resonator and a coherence time of about 10 μs was obtained.
② Research and development of bosonic cords using superconducting resonators
Error-correcting codes, called bosonic codes, are a method of protecting quantum information from errors by utilizing the degrees of freedom of the energy levels of resonators, which are in principle infinite, and are expected to reduce the number of physical qubits actually required as hardware compared to conventional methods. By the previous fiscal year, Q values exceeding the eighth power of 10 had been obtained in the prototype 3D (cavity) resonator, which were equal to or better than those of the previous study. This year, we optimized the design of bosonic qubits and improved the characteristics of ancilla qubits. By improving the design and fabrication method of ancilla qubits, we were able to achieve coherence times of tens of microseconds with good reproducibility, creating an environment in which bosonic qubits can be implemented. As a first step, we have successfully observed the spectral splitting of auxiliary qubits according to the number of photons in the storage cavity.
3. Future Directions
Regarding the development of a large-area, high-throughput Josephson junction fabrication technology, we aim to establish a fabrication method for qubits that does not use angle deposition. In parallel, we will work on reducing the variation of qubits and improving the coherence time. For the bosonic code, we will implement the binominal code in the resulting resonator, and in parallel, we will proceed with a prototype niobium resonator to achieve an even higher Q-value.