Summary of the project

In order to realize a quantum error tolerant general-purpose quantum computer, it is necessary to improve both "quality" and "quantity" aspects of quantum computers. While the current development of quantum computers is dominated by a bottom-up approach that prioritizes "quality" and increases the number of qubits, this project will take the opposite top-down approach. In other words, in order to take advantage of the advanced integration capability of silicon semiconductor technology (i.e., the ability to implement a large number of elements with uniform characteristics), we will promote a system design that emphasizes "quantity" from the beginning. Next, we will develop various technologies (two-dimensional qubit arrays, cryogenic CMOS circuits and mounting systems, hot silicon qubits, digital correction, etc.) made possible by this high silicon integration to improve the "quality" of the system as a whole and realize an error-resistant general-purpose quantum computer.

Milestone by year 2030

We will launch an experimental cloud service that will enable large-scale silicon quantum computers and demonstrate the effectiveness of error correction and silicon quantum computers.

Milestone by year 2025

We will develop a two-dimensional qubit array and demonstrate qubit operations on a silicon quantum computer using this array.

R&D theme progress reports

• 1. Quantum Computing System
• 2. Multi-chip cryogenic packaging technology
• 3. Hot silicon qubits
• 4. Quantum computing in small qubit systems

R&D theme structure of the project

Leader's institution

Hitachi, Ltd.

R&D institutions

Kobe University, Tokyo Institute of Technolog, RIKEN

PDF Download

• Summary of the project (323KB)
• Progress Report (Download all) (985KB)

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