Takashi Arikawa

Development of semiconductor terahertz comb oscillator by integrated use of electronics and photonics

Grant No.：JPMJPR21B1

Researcher

Takashi Arikawa

Outline

The objective of this study is to develop a semiconductor based broadband terahertz comb oscillator by integrated use of electronics and photonics. Specifically, concepts in laser technology will be introduced to electronic oscillators based on resonant tunneling diode to push the limits of the conventional technologies. This research will contribute to the realization of a safe and secure society by accelerating the spread of novel sensing technologies that use terahertz wave as an information carrier.

Shun Kanai

Non-deterministic spintronics device

Grant No.：JPMJPR21B2

Researcher

Shun Kanai

Outline

By elucidating the material and structural properties related to the operating principles of spintronics stochastic bit devices as well as by creating quantum functions therein, this project aims to overcome the physical limits of conventional deterministic computing. By bridging a gap between magnetic spintronics research and quantum spin research in terms of materials, physical scales, and hardware, the project will develop fundamental technologies essential for the realization of a world-leading “super-smart society.”

Satoshi Kawakami

Noise-driven ultra-low-power computing with single flux quantum devices

Grant No.：JPMJPR21B3

Researcher

Satoshi Kawakami

Outline

This research proposes a calculation principle and single flux quantum circuits that utilizes noise as a circuit operation mechanism to break through the noise limit which is the rate-determining factor for power reduction. Based on the noise-driven elements, I design arithmetic circuits with reversible logic gates and a computer system architecture integrated with clock-drived circuits to create an ultra-low power computing platform for an advanced information society.

Atsutake Kosuge

Device-System co-designed ultra-low voltage wired-logic AI processor

Grant No.：JPMJPR21B4

Researcher

Atsutake Kosuge

Outline

An energy-efficient AI processor is a key technology to realize cyber-physical systems in Society 5.0. The technical challenge of the conventional AI processor is the large power consumption of the memory access. The goal of this project is to develop a wired-logic AI processor to improve energy efficiency by a factor of the order of magnitude, where the data is directly transferred between processing elements without the memory access similar to the human brain. By co-designing the device/system/algorithm, we will design an energy and area efficient processor.

Tomohiro Koyama

Innovative information control in memory device based on magnetic domain wall motion using local modulation of magnetic properties

Grant No.：JPMJPR21B5

Researcher

Tomohiro Koyama

Outline

In this project, the magnetic domain in the magnetic wires, which are the infromation carrier in the domain wall memory devices, are efficiently controlled using the local modulation of magnetic properties. The goals of this project: 1. to show high-density and low-energy magnetic domain writing, 2. to demonstrate domain wall inverter operation using electrically-induced chiral spin structure. This study contributes to create new information processing technique, which makes magnetic memory devices high-density and low-power consumption.

Shigehisa Shibayama

Development of Teraheltz device using heterojunction composed of non-equilibrium group-IV semiconductors

Grant No.：JPMJPR21B6

Researcher

Shigehisa Shibayama

Outline

In this study, we will firstly develop resonant tunnel diode (RTD) device using GeSiSn/GeSn heterojunction, which has shown the hole resonance phenomena, and characterize its operating properties. On the basis of this demonstration result, (1) we will clarify the design guidelines for device structures enabling stable operation from both experimental and theoretical perspectives. Also, (2) to improve the reliability of RTD device operation, we will develop elemental technologies for controlling Ge(Si)Sn crystal defects and insulater/Ge(Si)Sn interface defects. Finally, we will demonstrate room temperature operation of GeSiSn/GeSn heterojunction RTD devices.

Seiya Suzuki

Development of germanene devices using interfacial segregation technology and exploration of their function

Grant No.：JPMJPR21B7

Researcher

Seiya Suzuki

Outline

Although germanene, a two-dimensional germanium crystal with a single atomic layer, is expected to have new topological properties, the prospects for its device application are not clear at all. This is due to the chemical instability of germanene, which makes it very difficult to establish a robust method for developing germanene devices. In this research, I will fabricate germanene electronic devices by improving the interfacial growth techniques of germanene, and investigate and explore their properties and functions.

Miyuki Tabata

Development of a liquid biopsy platform based on ionoelectronics

Grant No.：JPMJPR21B8

Researcher

Miyuki Tabata

Outline

In this research, by fabricating a SiNW-FET having a well structure with an opening of 200-300 nm and functionalizing the sensor interface, single extracellular vesicle analysis is performed. On the accuracy of distinguishing extracellular vesicles derived from epithelial cells and cancer cells, it aims to be 90% or more. The process of this electrical detection involves movements of information carriers such as molecular recognition, ion generation, and changes in charge density of the channel, and this research trys to develop a future liquid biopsy platform that quantitatively displays the amount of change in information carriers.

Hiroki Morishita

Development of NV quantum spintronics fundamental technologies for connecting classical and quantum information

Grant No.：JPMJPR21B9

Researcher

Hiroki Morishita

Outline

To realize Society 5.0, etc., quantum information carriers that can connect classical information in physical space with quantum information in cyberspace and have the ability to convert classical information to quantum information and vice versa are needed. In this project, I will develop novel NV quantum spintronics technologies to convert classical to quantum information and vice versa using electrical techniques of NV quantum information carriers operating at room temperature.

Jun Yoneda

Exploration of network-on-chip silicon quantum processors

Grant No.：JPMJPR21BA

Researcher

Jun Yoneda

Outline

Fault-tolerant quantum computation has potential to revolutionize information processing speed, which is otherwise approaching its limits. This project will pursue a silicon-based quantum processing architecture that will overcome the two major hurdles to realizing fault-tolerant quantum computation - wiring and quantum error correction - at the same time. The goal is to create an on-chip quantum network in silicon based on the electron spin qubit transport technique as a novel operating mechanism for a truly scalable quantum processor with information encoded by quantum states of electron spins.