Hiromitsu Awano

Pioneering Human-Machine Co-Existence Society: Explainable Deep Learning for Safety Intelligence

Researcher

Hiromitsu Awano

Outline

This research explores a novel computing technique based on a gate level self-synchronous circuit (GLSSC) and a bit-serial architecture to accelerate explainable artificial intelligence (AI) algorithms for an improved human-machine cooperation. Due to aggressive transistor scaling, the variability of transistors continues to increase rapidly, which makes classical synchronous circuits as quite inefficient. To fully eliminate the timing margin required in the synchronous circuits, this research focuses on GLSSC, where each logic gate makes handshaking for data transmission. GLSSC technology is combined with a bit-serial architecture to strike the best tradeoff between silicon area and delay. Finally, the fabricated GLSSC chip is embedded onto a robot-vehicle to demonstrate an improved power efficiency and reduced latency applicable for a real-time operation.

Sosuke Ito

Stochastic thermodynamics and information geometry for a biological computation

Researcher

Sosuke Ito

Outline

This research aims to construct the unified theory between stochastic thermodynamics and information geometry for several bio-inspired computings such as neuromorphic computing.This research also aims to a numerical application of the unified theory for experimental neural data.

Rei Ueno

Development of Post-Quantum Cryptographic Modules for Battery-Less Wireless Sensor Network

Researcher

Rei Ueno

Outline

This research develops technologies to compute Post-Quantum Cryptography (PQC) for the long-term security of battery-less wireless sensor network. Wireless sensor network has been utilized in many Internet of Things (IoT) applications including self-driving car, smart home/factory, and self-check of infrastructures. On the other hand, some of such applications should work without battery by means of energy-harvesting and require very long-term security for maintenance-freeness and standardization. Hence, this research develops technologies for securely and efficiently computing PQC. The PQC modules will be designed to be implementable to even resource-constraint IoT devices in order to realize the security of battery-less wireless sensor network even after the development of practical quantum computers.

Jun OHKUBO

Computing technology based on dual processes

Researcher

Jun OHKUBO

Outline

To make information infrastructures supporting a super-smart society, it is necessary to realize new computing technology that qualitatively changes the information processing. In this research project, I propose a new computing principle which utilizes a mathematical property of duality in stochastic processes. This computing principle gives us a new computing framework in which pre-computations for dual processes give high-speed computations of time-evolution for original processes at execution. This research project realizes highly efficient edge-processing in research subjects of filtering, control, and machine learning, which will contribute to the IoT era.

Naoya Onizawa

Study of Invertible Logic for Edge-Type Learning Hardware

Researcher

Naoya Onizawa

Outline

This research is to develop fundamental technologies of ultra-low power AI for super smart society. For this purpose, learning processes of deep neural networks currently running on cloud servers try to be realized by a proposed edge-type learning hardware. The proposed learning hardware can be implemented based on new-paradigm computing that is a combination of stochastic computing and invertible logic.

Yukinori Sato

Dataflow centric integration and orchestration of custom computing systems

Researcher

Yukinori Sato

Outline

For realizing a human-centered super smart society called Society 5.0, it is very important to attain high-performance and high-efficiency computing through custom computer systems specialized for particular application domains. On the other hand, customization of systems incurs challenges in productivity and costs for the hardware and software development process. In this project, we propose a dataflow centric orchestration technique for custom computing system designs and integrations. We focus on dataflow based FPGA accelerators and a domain specific language for dataflow computing, and attempt to realize highly efficient performance per watt ratio in a productive manner.

Renyuan ZHANG

Single-Wire Driven Efficient Approximate Computing Technologies

Researcher

Renyuan ZHANG

Outline

This project aims at developing novel computing fundamentals on the basis of single-wire-driving data representations. Various computing architectures are explored for the next generation in the Post-Moore era. The general purpose computational processors are expected to achieve high speed and efficiency without the direct benefits from scaling-down of semiconductor devices. Escaping from the conventional binary presentations and deductive computations, the hardware implementing approximate computations is developed through soft-computing technologies such as regression and statistics. The final target is innovating the computing architectures in the near future.

Hideki Takase

A comprehensive IoT system development environment for the realization of data oriented development paradigm

Researcher

Hideki Takase

Outline

This research aims for the realization of a paradigm shift in IoT system development by exploring the possibility of functional programming language to place emphasis on processing and communication for big data. In order to improve execution efficiency and development productivity of IoT systems, we will construct an innovative system-level development framework that includes the components and design hierarchy of the IoT system architecture.

Shinya Takamaeda

Highly Efficient Deep Learning System by Architecture/Algorithm Co-Design

Researcher

Shinya Takamaeda

Outline

This project aims to develop cooperative approaches of computer architecture and algorithm for realtime deep learning systems with reliable recognition and online training capability on edge computing platforms. We will identify the best mix of architecture and algorithm that maximize the accuracy, speed, energy efficiency, and reliability of the system based on collaboration of cooperative algorithm for efficient but restricted architecture, and computer architecture support for flexible algorithm implementation. We will also develop a high-level synthesis hardware compiler for rapid implementations of the proposed architecture and algorithm technologies.

Noriyuki MIURA

Triturated Computing System

Researcher

Noriyuki MIURA

Outline

In this research, a miniaturized computer even swallowable like powdered medicine, namely Triturated Computing System (TCS) is proposed. All the computing component blocks are separately diced and hence extremely downsized to 0.1mm-side per chip. These triturated components are clustered to form high-performance computing system. The goal of this research is to develop fundamental enabling technologies for this TCS and realize an emerging computer architecture non-invasively and unconsciously integrated into human life and society.

Hideaki Yamamoto

In vitro reconstruction of bionic computing systems

Researcher

Hideaki Yamamoto

Outline

How does a complex network of excitable cells realize robust and energy-efficient computation in the brain? This research will integrate semiconductor microfabrication, in vitro cell-culture experiments, and mathematical modeling to constructively exploit the mechanism of how living neurons form networks, give rise to high-dimensional dynamics, and perform information processing. By linking multi-cellular dynamics of engineered neuronal networks to computation, biologically-inspired models of neurons and neuronal systems will be established for future implementation in next-generation neuromorphic systems.