Summary of the project

This project aims to construct a co-design model encompassing qubit design, fault-tolerant architecture, and compilers and programming languages for efficient computation through collaborations of researchers in quantum information, architecture, and specific physical systems, thereby endeavoring to realize a large-scale quantum computer by the year 2050.

Milestone by year 2030

We will deliver a significant reduction in hardware requirements for realizing a large-scale fault-tolerant quantum computer.

Milestone by year 2025

We will develop a supporting tool for designing a fault-tolerant quantum computer with integration of hardware and software.

R&D theme progress reports

• 1. Development and expansion of cross-layer codesign models
• 2. Development of hardware control methods and analysis of performance
• 3. Development of quantum error correction schemes and analysis of performance
• 4. Research and development of distributed fault-tolerant quantum computers

R&D theme structure of the project

To expedite the theoretical research, the project members of the R&D institutes are collaborating with each other beyond the assigned themes shown above and tackling the problems with their open minds

Leader's institution

Univ. of Tokyo

R&D institutions

NTT, U of Tokyo, U of Tsukuba, TMDU, RIKEN, Osaka U, OIST, Keio U, Kyoto U, UEC, AIST

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• Summary of the project (285KB)
• Progress Report (Download all) (687KB)

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