Modeling, Detection, Correction and Recovery Techniques for Unified Dependable Design

Research Project Outline

The goal of the project is to establish a design flow in system and RT levels for dependable digital VLSI. We will define models errors and indexes of dependability, and develop techniques to evaluate the indexes and to improve them. We will implement the techniques as design and analysis tools, and combine the tools into an existing design flow to make a prototype of design flow in which designers can consider tradeoffs among cost, performance, power consumption and dependability.

Related Links

• Laboratory Website: http://www.c.csce.kyushu-u.ac.jp/SOC/index.html