- Ferroelectric HfO2-based transistor and memory are expected to realize ultralow power electronics, however, their operation mechanism and scalability were not clarified yet.
- Physical mechanism of low voltage operation of a transistor with ferroelectric-HfO2 gate insulator has been experimentally clarified. Scalability of ferroelectric memory with HfO2 tunnel-layer down to 20nm diameter has been theoretically elucidated.
- The obtained results will contribute to enabling ultralow power IoT device and thus highly sophisticated network services.
As a part of JST PRESTO program, Associate professor Masaharu Kobayashi, Institute of industrial Science, The University of Tokyo, has experimentally clarified the operation mechanism of low voltage operation of a transistor with ferroelectric-HfO2 gate insulator. In addition, he has theoretically elucidated scalability of ferroelectric tunnel junction (FTJ) memory with ferroelectric-HfO2 down to 20nm diameter.
Negative capacitance FET (NCFET) with ferroelectric-HfO2 gate insulator is attracting interests as a steep subthreshold slope transistor for ultralow voltage operation, which can break the physical limit of 60mV/dec in the conventional MOSFET. However, its operation mechanism has not been fully clarified yet in terms of polarization switching dynamics. FTJ memory with ferroelectric-HfO2 is a promising high-capacity nonvolatile memory. However, its scalability considering resistance ratio between read current for access speed, resistance ratio between on-state and off-state for sensing margin, depolarization field for retention characteristics has not been fully elucidated yet.
In this study, he has experimentally demonstrated sub-60mV/dec subthreshold slope in a transistor with ferroelectric-HfO2 and clarified that the physical mechanism is attributed to charge injection assisted by polarization switching in ferroelectric-HfO2 gate insulator improves subthreshold characteristics as shown in Fig. 1. Furthermore, he has systematically investigated the relationship between subthreshold characteristics and polarization switching by monitoring gate current with high resolution and clarified that polarization switching dynamics causes transient negative capacitance by depolarization effect due to small depletion layer capacitance, as shown in Fig. 2.
As for FTJ, he has established non-equilibrium Green function method with self-consistent potential involving polarization charge and semiconductor surface potential to calculate current through FTJ memory. This simulation framework is calibrated by experimental results of ferroelectric-HfO2 FTJ memory in the form of metal-ferroelectric-semiconductor structure, which was previously developed and demonstrated in the same JST PRESTO program. By utilizing this simulation framework, he has theoretically predicted that ferroelectric-HfO2 FTJ can be scaled down to 20nm diameter size by systematically investigating the impacts of material properties and considering the trade-off among read current for access speed, resistance ratio between on-state and off-state for sensing margin, and depolarization field for data retention characteristics, as shown in Fig. 3.
The achievements in this study will largely contribute to guiding device design of ultralow power operating NCFET and high-capacity FTJ memory, which leads to enabling ultralow power IoT edge devices, deploying highly sophisticated network system, and thus providing more strategic social services utilizing big data.
This work was presented in IEEE International Conference on Electron Device Meeting on December 4th and 5th in 2018, which was held in San Francisco.
Fig. 1 Drain current versus gate voltage characteristics of metal-ferroelectrie-metal-insulator-semiconductor type FET with 30% Zr-doped HfO2 gate insulator. By switching gate bias direction at polarization switching, steep subthreshold slope less than 30mV/dec was clearly observed.
Fig. 2 Drain current versus gate voltage characteristics of metal-antiferroelectric-metal-insulator-semiconductor type FET with 90% Zr-doped HfO2 gate insulator for area ratio of top and bottom electrodes of (left) 1:8, (center) 1:14, and (right) 1:32, respectively. For example, in the center figure, polarization switching does not happen in subthreshold region in forward sweep, however, polarization switching does happen in subthreshold region in backward sweep and thus subthreshold slope becomes steeper than in forward sweep.
Fig. 3 Simulated relationship between resistance ratio at on-state and off-state, required ferroelecric-HfO2 thickness, and memory cell diameter for targeting (left) 10nA read current and (right) 100nA read current, respectively. For such read current target, FTJ memory cell can be scaled down to 2nm diameter as long as ferroelectricity is maintained at 1~1.5nm film thickness.
Research Area “Innovative Nano-electronics through Interdisciplinary Collaboration among Material, Device and System Layers”
Research Theme “Research and development of steep slope transistor using negative capacitance of gate insulator for ultralow power operation and its application to nanowire structure”
Associate professor, Institute of industrial Science, The University of Tokyo
Department of Innovation Research, JST