A new tunneling field effect transistor (TFET) has been proposed and experimentally demonstrated by utilizing a new material combination of oxide semiconductors and group-IV semiconductors such as Si, SiGe and Ge with type-II energy band alignment. The proposed device has a high potential for ultra-low voltage operation with a record-high on-current/ off-current ratio through effective enhancement of tunneling probability in the above material combination, which is expected to reduce power consumption of IoT devices drastically.
Program Information
JST CREST
Research Area “Innovative Nano-electronics through Interdisciplinary Collaboration among Material, Device and System Layers”
Research Theme “Development of Tunneling MOSFET Technologies for Integrated Circuits with Ultra-Low Power Consumption”
Journal Information
Kimihiko Kato, Hiroaki Matsui, Hitoshi Tabata, Mitsuru Takenaka, and Shinichi Takagi, “Proposal and demonstration of oxide-semiconductor/(Si, SiGe, Ge) bilayer tunneling field effect transistor with type-II energy band alignment, Technical Digest of IEEE International Electron Device Meeting (IEDM), p. 377, (Date for publish and doi: not yet determined)
Contact
[About Research]
Shinichi Takagi, Ph.D.
Professor, School of Engineering, The University of Tokyo
E-mail: 
[About Program]
Tsuyoshi Nakamura
Green Innovation Group, Department of Innovation Research, JST
E-mail: 