Achieving energy-efficient AI processors with a single photomask

A research group led by Associate Professor Atsutake Kosuge of the Graduate School of Engineering at the University of Tokyo has developed a new structured-ASIC -based AI processor that is both low cost and energy efficient (Fig. 1). Structured ASIC refers to a method in which basic circuits are pre-embedded in a semiconductor substrate, and the desired functionality is achieved with minimal wiring added.

In semiconductor manufacturing, a template called a photomask is needed to transfer circuits onto the surface of a semiconductor. Conventional AI processors require several dozen photomasks, but with this new method, just one photomask suffice. Until now, the development of photomasks has cost tens of billions of yen, but the group has succeeded in reducing this to 1/40th. The prototype measures less than 9 mm², consumes low power, and is able to perform processes such as EEG analysis and ECG analysis.

The challenge of achieving both low cost and low power consumption

AI technology is expected to bring transformative changes to a variety of industrial sectors and to enrich people's daily lives. In particular, wearable devices are known to contribute to the early detection of diseases by analyzing information such as brainwaves and heart rate using AI. However, when it comes to wearable devices, which must be worn on the body, the development of AI processors that operate at low cost and with low power consumption has become a major challenge. In order to reduce the size and weight, battery-powered operation is essential, and furthermore, it must be inexpensive.

Before now, AI processors designed for low power consumption have been developed. However, in order to reduce power consumption, those processors had to be specialized for specific functions, losing their general-purpose capabilities. For this reason, existing photomasks could not be reused but had to be manufactured for each application. In order to recover the development cost of photomasks, which can reach tens of billions of yen, the only option has been to set high prices for AI processors, making it difficult to realize both low cost and low power consumption simultaneously.

Technology developed to reduce photomask count and chip area

Reducing the required photomasks to just one

The structured ASIC method is a manufacturing approach for AI processors in which the basic circuits and wiring are pre-fabricated on the chip, and only the upper-layer interconnects in the final stage are custom-designed or changed according to the intended purpose. The research group enhanced this approach by developing Via-programmable Neuron Array technology, which realizes specific functions through the customization of just one layer of the processor. As a result, only one photomask is necessary, significantly reducing development costs.

Sharing circuits and wiring to reduce the implementation area

However, applying deep neural network models^*1, the core of AI technology, to this type of processor requires dedicated circuits and a massive number of signal interconnects to transmit information for each individual function, and incorporating these would exceed the feasible implementation area, posing a significant challenge.

Instead of preparing dedicated circuits and signal interconnects for each function, the research group developed bit- and neuron-serial circuit technology that reuses circuits and wiring across multiple processes via switching, thereby reducing the number of signal interconnects to 1/1024. Furthermore, the group reduced the weight coefficients^*2 of deep neural networks from 16 bits (i.e., 65,536 possible values) to 3 values: +1, −1, and 0. This successfully reduced wiring complexity while preventing degradation in AI accuracy.

*1 Deep neural network model
A computational AI model for distinguishing complex patterns and features

*2 Weight coefficient
A value indicating the degree of influence of an input on the output

Achieving a low-cost and low-power AI processor

As a result of combining these technologies, the group achieved an AI processor that can be manufactured with a single photomask, operates at low power, and occupies a small circuit area of less than 9 mm². Specifically, compared to conventional AI processors, the development cost was reduced to 1/40, and power consumption was reduced to 1/8.4 (Fig. 2).

Further expansion of AI application areas

The novel AI processor developed in this research features low-cost creation and low-power operation and is expected to be used in wearable devices such as smartwatches and AR/VR devices. Furthermore, this technology is expected to expand the potential for AI utilization, even in fields where implementing AI has been difficult due to cost and energy constraints.