Ferroelectric FET (FeFET) is a promising memory device because of its low-power, high-speed and high-capacity. Toward 3D integration for higher capacity, a team of researchers has developed a ferroelectric-HfO₂ based FeFET with 8nm-thick IGZO channel instead of poly-silicon channel. They achieved nearly ideal subthreshold swing of 60mV/dec and higher mobility than poly-silicon channel thanks to the material property of IGZO and junctionless transistor operation. The obtained results will contribute to ultralow power devices for IoT applications.

As a part of JST PRESTO program, Associate professor Masaharu Kobayashi, Institute of Industrial Science, the University of Tokyo, has developed a ferroelectric FET (FeFET) with ferroelectric-HfO₂ and ultrathin IGZO channel. Nearly ideal subthreshold swing (SS) and mobility higher than poly-silicon channel have been demonstrated.

FeFET is a promising memory device because of its low-power, high-speed and high-capacity. After the discovery of CMOS-compatible ferroelectric-HfO₂ material, FeFET has been attracting more attentions than ever before. For even higher memory capacity, 3D vertical stack structure has been proposed as shown in Fig. 1(a).

For 3D vertical stack structure, poly-silicon is typically used as a channel material. However, poly-silicon has very low mobility in nanometer thickness region due to grain boundaries and extrinsic defects. Moreover, poly-silicon forms a low-k interfacial layer with ferroelectric-HfO₂ gate insulator. This results in voltage loss and charge trapping which prevents low voltage operation and degrades reliability, respectively as shown in Fig. 1(b).

To solve these problems, in this study, we proposed a ferroelectric-HfO₂ based FeFET with ultrathin IGZO channel. IGZO is a metal-oxide semiconductor and can avoid low-k interfacial layer with ferroelectric HfO₂ gate insulator. Moreover, since IGZO is N-type semiconductor and typically used in junctionless transistor operation, charge trapping, which seriously happens in inversion mode operation, can be avoided as shown in Fig. 1(b).

First, we systematically investigated optimum IGZO channel thickness. As IGZO thickness decreases, SS is reduced and threshold voltage (Vth) increases. To realize steep SS and normally-off operation, 8nm was chosen. Next, we fabricated TiN/HfZrO₂/IGZO capacitor. HfZrO₂ is the ferroelectric layer. Cross-sectional TEM image shows that each layer was uniformly formed as shown in Fig. 2(a). GIXRD spectrum was taken and ferroelectric phase was confirmed. By electrical characterization, we confirmed clear ferroelectric property with IGZO capping on HfZrO₂ as shown in Fig. 2(b). It should be noted that, in the current device design, back-gate is needed with buried oxide to fix body potential. Without back-gate, body potential is floating and voltage cannot be sufficiently applied on ferroelectric-HfO₂ gate insulator, which was confirmed by TCAD simulation. Based on these device design, we fabricated a FeFET with ferroelectric-HfO₂ and ultrathin IGZO channel. Fig. 3(a) shows the measured drain-current versus gate-voltage after applying write and erase pulse voltages. 0.5V memory window and nearly ideal SS of 60mV/dec was obtained. In addition, field-effect mobility is about 10cm²/Vs as shown in Fig. 3(b), which can be higher than poly-silicon at the same thickness.

The achievements in this study will open a new path for realizing low-voltage and highly reliable FeFET with 3D vertical stack structure. This leads to enabling ultralow power IoT edge devices, deploying highly sophisticated network system, and thus providing more strategic social services utilizing big data. This work was presented in VLSI Technology Symposium 2019 on June 11th in 2019, which was held in Kyoto, Japan.