A new transistor using tunneling current, which can operate at ultra-low power consumption and can lead to significant reduction in the power of IT instruments, has been successfully developed by utilizing junctions composed of strained-Silicon and Germanium.
Researcher Information
JST CREST
Research Area “Innovative Nano-electronics through Interdisciplinary Collaboration among Material, Device and System Layers”
Research Theme “Development of Tunneling MOSFET Technologies for Integrated Circuits with Ultra-Low Power Consumption”
Journal Information
Minsoo Kim, Yuki Wakabayashi, Ryosho Nakane, Masafumi Yokoyama, Mitsuru Takenaka, and Shinichi Takagi. “High Ion/Ioff Ge-source ultrathin body strained-SOI Tunnel FETs-impact of channel strain, MOS interfaces and back gate on the electrical properties”. Tech. Dig. International Electron Device Meeting (IEDM) —Technical digest of presentations in IEDM, the largest international conference on semiconductor device and process technologies hosted by IEEE (The Institute of Electrical and Electronics Engineers, Inc.), to be published in six months or more, doi: not yet determined.
Contact
[About Research]
Shinichi Takagi Ph.D.
Professor, School of Engineering, The University of Tokyo
E-mail: 
URL: http://www.mosfet.k.u-tokyo.ac.jp/index-e.html
[About Program]
Masashi Furukawa
Green Innovation Group, Department of Innovation Research, JST
E-mail: 