SiC power devices are expected to contribute to energy savings. However, the performance of them has been severely limited by the defects formed at the interface between SiC and gate dielectric film. The research group of associate professor, Koji Kita at the University of Tokyo, has successfully developed a device fabrication technique to minimize the defect density at the interface, to boost the device performance of SiC transistor toward its theoretically expected one. This technique is expected to accelarate the spread of SiC power devices through the improvement of their performances and reliabilities.
Researcher Information
JST PRESTO
Research Area: “Phase Interfaces for Highly Efficient Energy Utilization”
Research Theme: “Interface Engineering for High Performance SiC MOSFETs with Low On-state Resistance”
Journal Information
Author: Richard Heihachiro Kikuchi and Koji Kita
Title: “Fabrication of SiO2/4H-SiC (0001) Interface with Nearly-Ideal Capacitance-Voltage Characteristics by Thermal Oxidation”
Applied Physics Letters, Published online 28 July 2014
doi: 10.1063/1.4891166
Contact
[About Research]
Koji Kita, Ph.D.
Associate Professor, Department of Materials Engineering, Graduate school of Engineering, The University of Tokyo
E-mail: 
URL: http://www.scio.t.u-tokyo.ac.jp/top-eng.html
[About Program]
Koji Matsuo, Masashi Furukawa, and Hisao Mizuta
Green Innovation Group, Department of Innovation Research, Japan Science and Technology Agency
E-mail: 