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Materials and processes for innovative next-generation devices
Researchers & Research Theme
Phase I Phase II Phase III

2007 Researchers

Seiya KASAI Eiji SAITOH Masashi SHIRAISHI
Y.K. TAKAHASHI Tomoyasu TANIYAMA Arata TSUKAMOTO
Naoki FUKATA Shuichi MURAKAMI Takeshi YASUDA
Akinobu YAMAGUCHI Katsunori WAKABAYASHI  

Development of semiconductor nanowires for the realization of vertical three-dimensional semiconductor devices

photo Naoki FUKATA
Research Site
Group Leader of Nanostructured Semiconducting Materials Group International Center for Materials Nanoarchitectonics (MANA), National Institute for Materials Science
URL
http://www.nims.go.jp/jpn/org/field03-1aemc.html
Research Results
Advances in performance and integration through conventional scaling of device geometries are now reaching their practical limits in planar MOSFETs. To overcome the limiting factors in planar MOSFETs, vertical structural arrangements called surrounding gate transistors (SGT) have been suggested as the basis for next-generation semiconductor devices. In this study, I study one dimensional semiconductor nanowires which are expected for the components in SGT.



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