Technology Innovation and Integration for Information Systems with Ultra Low Power

Outline

This research aims at breaking the limitations associated with lowering the power consumption of existing technologies by performing hierarchical administration and control of the circuits and devices, the architecture, the system software, the algorithms and the protocols, as well as the application and the services related to information transmission systems and networks. Specifically, this field includes research aiming to achieve low power consumption and dramatic improvement in the performance and reliability of technologies for dynamic voltage control, adaptive energy management technologies, dynamically reconfigurable architectures, power-efficient algorithms and network architectures, compilers and programming languages for parallel processing, and other individual elemental technologies. The field also involves research to provide breakthroughs in the drastic lowering of system power consumption by implementing integrated administration of the elemental technologies at each level of the hierarchy, as well as by developing fundamental software and hardware technologies based on new principles which can achieve dramatic reductions in power consumption.

Strategic Sector

Creation of Ultra-low Power Technologies to Cope with Explosive Increase in Electric Power Consumption in the Future Society

Research Projects

Year Started : 2007
Research Director	Affiliation	Research Project
Haruhisa Ichikawa	Professor, The University of Electro-Communications	Strategic Integration of Ultra-Low Power Systems for Ambient Intelligence
Hiroaki Nishikawa	Professor, University of Tsukuba	Ultra-Low-Power Data-Driven Networking System
Ryutaro Maeda	Director, National Institute of Advanced Industrial Science and Technology (AIST)	Optimum Control of Electrical Power in IT Systems by ULP Networked Sensing Systems
Satoshi Matsuoka	Professor, Tokyo Institute of Technology	ULP-HPC: Ultra Low-Power, High-Performance Computing via Modeling and Optimization of Next Generation HPC Technologies

Year Started : 2006
Research Director	Affiliation	Research Project
Hanpei Koike	Group Leader, National Institute of Advanced Industrial Science and Technology (AIST)	Development of Ultra-low-power FPGA with Fine-Grained Field-Programmable Threshold Voltage Control
Satoshi Goto	Professor, Waseda University	Research on Ultra Low Power SoC for Media Processing
Naofumi Takagi	Professor, Kyoto University	Low-power, High-performance, Reconfigurable Processor Using Single Flux Quantum Circuits
Hiroshi Nakamura	Professor, The University of Tokyo	Innovative Power Control for Ultra Low- Power and High-Performance System LSIs

Year Started : 2005
Research Director	Affiliation	Research Project
Tadahiro Kuroda	Professor, Keio University	Generation of High-performance, Ultra-low-power, Short-range Wireless Mobile Information System
Hikaru Kobayashi	Professor, Osaka University	Extremely Low Power System Display by Use of Fine Gate Structure
Ken-ichi Sato	Professor, Nagoya University	Optical Routing Network Technologies that Enable Ultra-Low Power Consumption
Hiroaki Takada	Professor, Nagoya University	Hardware/Software Co-Optimization for Low-Energy Embedded Systems

Research Area Website: http://www.ulp.jst.go.jp/